The present invention relates to the field of manufacturing semiconductor devices and, more particularly, to an improved salicide process of forming metal silicide contacts.
An important aim of ongoing research in the semiconductor industry is the reduction in the dimensions of the devices used in integrated circuits. Planar transistors, such as metal oxide semiconductor (MOS) transistors, are particularly suited for use in high-density integrated circuits. As the size of the MOS transistors and other active devices decreases, the dimensions of the source/drain regions and gate electrodes, and the channel region of each device, decrease correspondingly.
The design of ever-smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junctions. Shallow junctions are necessary to avoid lateral diffusion of implanted dopants into the channel, since such a diffusion disadvantageously contributes to leakage currents and poor breakdown performance. Shallow source/drain junctions, for example on the order of 1,000 xc3x85 or less thick, are generally required for acceptable performance in short channel devices.
Shallow source/drain junctions have corresponding shallower source/drain extensions. As the depth of the junction decreases, the electrical resistivity of the junction increases. This increase in resistivity is particularly a problem in shallow source/drain extensions. The high resistivity of shallow source/drain regions and extensions is alleviated by supersaturating the dopant concentration in the source/drain regions and extensions. In addition, the resistivity of the source/drain regions is temperature dependent. Supersaturating the source/drain regions and extensions reduces the resistivity temperature dependence.
Metal silicide contacts are typically used to provide low resistance contacts to source/drain regions and gate electrodes. The metal silicide contacts are conventionally formed by depositing a conductive metal, such as titanium, cobalt, tungsten, or nickel, on the source/drain regions and gate electrodes by physical vapor deposition (PVD), e.g. sputtering or evaporation; or by a chemical vapor deposition (CVD) technique. Subsequently, heating is performed to react the metal with underlying silicon to form a metal silicide layer on the source/drain regions and gate electrodes. The metal silicide has a substantially lower sheet resistance than the silicon to which it is bonded. Selective etching is then conducted to remove unreacted metal from the non-silicided areas, such as the dielectric sidewall spacers. Thus, the silicide regions are aligned only on the electrically conductive areas. This self-aligned silicide process is generally referred to as the xe2x80x9csalicidexe2x80x9d process.
A portion of a typical semiconductor device 50 is schematically illustrated in FIG. 1A and comprises a silicon-containing substrate 10 with source/drain regions 26 formed therein. Gate oxide layer 14 and gate electrode 16 are formed on the silicon-containing substrate 10. Sidewall spacers 34 are formed on opposing side surfaces 18 of gate electrode 16. Sidewall spacers 34 typically comprise silicon based insulators, such as silicon nitride, silicon oxide, or silicon carbide. The sidewall spacers 34 mask the side surfaces 18 of the gate 16 when metal layer 36 is deposited, thereby preventing silicide from forming on the gate electrode side surfaces 18.
After metal layer 36 is deposited, heating is conducted at a temperature sufficient to react the metal with underlying silicon in the gate electrode 16 and substrate surface 12 to form conductive metal silicide contacts 38 (FIG. 1B). After the metal silicide contacts 38 are formed, the unreacted metal 36 is removed by etching, as with a wet etchant, e.g., an aqueous H2O2/NH4OH solution. The sidewall spacer 34, therefore, functions as an electrical insulator separating the silicide contact 38 on the gate electrode 16 from the metal silicide contacts 38 on the source/drain regions 26, as shown in FIG. 1B.
Various metals react with Si to form a silicide, however, titanium (Ti) and cobalt (Co) are currently the most common metals used to create suicides (TiSi2, CoSi2) when manufacturing semiconductor devices utilizing salicide technology.
Use of a TiSi2 layer imposes limitations on the manufacture of semiconductor devices. A significant limitation is that the sheet resistance for lines narrower than 0.35 micrometers is high, i.e., as TiSi2 is formed in a narrower and narrower line, the resistance increases. Another significant limitation is that TiSi2 initially forms a high resistivity phase (C49), and transformation from C49 to a low resistivity phase (C54) is nucleation limited, i.e., a high temperature is required to effect the phase change.
Cobalt silicide, unlike TiSi2, exhibits less line width dependence of sheet resistance. However, CoSi2 consumes significant amounts of Si during formation, which increases the difficulty of forming shallow junctions. Large Si consumption is also a concern where the amount of Si present is limited, for example, with silicon on insulator (SOI) substrates. Without enough Si to react with Co to form CoSi2, a thin layer of CoSi2 results. The thickness of the silicide layer is an important parameter because a thin silicide layer is more resistive than a thicker silicide layer of the same material, thus a thicker silicide layer increases semiconductor device speed, while a thin silicide layer reduces device speed.
One of the concerns recognized by the inventors in employing supersaturated source/drain extensions is their susceptibility to deactivation when exposed to moderately high temperatures, such as those typically employed in cobalt silicide or titanium silicide processing. High temperature annealing during the silicide formation step increases lateral and vertical diffusion of the dopants in the source/drain regions and extensions. Increased vertical diffusion of the dopant results in slower, deeper junctions, while increased lateral diffusion of the dopant can result injunction leakage. Furthermore, every time a wafer is heated and cooled crystal damage from dislocations occur. A high concentration of dislocations can cause device failure from leakage currents. For example, formation of CoSi2 contacts requires a two-step annealing process that includes a first annealing at approximately 500xc2x0 C. and a second annealing at approximately 800xc2x0 C. The 800xc2x0 C. annealing step is high enough to cause dopant diffusion, which lowers the electrical conductivity of the source/drain regions and extensions.
The term semiconductor devices, as used herein, is not to be limited to the specifically disclosed embodiments. Semiconductor devices, as used herein, include a wide variety of electronic devices including flip chips, flip chip/package assemblies, transistors, capacitors, microprocessors, random access memories, etc. In general, semiconductor devices refer to any electrical device comprising semiconductors.
Recently, attention has turned towards using nickel to form NiSi utilizing salicide technology. Using NiSi is advantageous over using TiSi2 and CoSi2 because many limitations associated with TiSi2 and CoSi2 are avoided. For purposes of this invention, one of the primary advantages of NiSi technology is the low processing temperatures employed. When forming NiSi, a low resistivity phase is the first phase to form, and does so at a relatively low temperature. Typically, the annealing temperature is between 400xc2x0 C. and 600xc2x0 C. Nickel silicide is normally annealed in a one step process, versus a process requiring an anneal, an etch, and a second anneal, as is normal for TiSi2 and CoSi2. Nickel silicide also exhibits low film stress, i.e., causes less wafer distortion.
There exists a need in the semiconductor device manufacturing art to provide a process of forming transistors with source/drain extensions having supersaturated dopant concentrations, without exposing the transistors to high processing temperatures in subsequent processing steps, such as forming silicide contacts.
These and other needs are met by the embodiments of the present invention, which provide a method of manufacturing a semiconductor device comprising providing a silicon-containing substrate, having an upper surface, with a gate insulating later and gate electrode formed on the substrate upper surface. The gate electrode has an upper surface and opposing side surfaces. Source/drain regions are formed in the substrate spaced apart from the gate electrode. Supersaturated dopant concentration source/drain extensions are formed in the substrate between the source/drain regions and the gate electrode. Metal silicide contacts are formed on the upper surfaces of the gate electrode and the substrate in a manner sufficient to maintain the supersaturated dopant concentration in the source/drain extensions.
The earlier stated needs are also met by other embodiments of the present invention that provide a semiconductor device comprising a silicon-containing semiconductor substrate having, an upper surface, with a gate insulating layer and a gate electrode formed on the upper surface of the substrate. The gate electrode has an upper surface and opposing side surfaces. Source/drain regions are formed in the substrate spaced apart from the gate electrode and supersaturated dopant concentration source/drain extensions are situated between the source/drain regions and the gate electrode. The gate electrode and the substrate have metal silicide contacts formed on their upper surfaces.
The earlier stated needs are further met by other embodiments of the instant invention that as provide a method of manufacturing a semiconductor device, the method comprising providing a silicon-containing semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate and a conductive gate material layer is formed over the gate oxide layer. The gate material layer and gate oxide layer is patterned to form a gate electrode having an upper surface and opposing side surfaces. A layer of insulating material is deposited over the gate electrode and the semiconductor substrate. The insulating material is patterned to form sidewall spacers on the opposing side surfaces of the gate electrode. Source/drain regions are formed by ion implanting a dopant into the substrate and heating the substrate to activate the source/drain regions. After forming the source/drain regions the sidewall spacers are removed. Supersaturated dopant concentration source/drain extension are formed between the gate electrode and source/drain regions. A second layer of insulating material is deposited over the gate electrode and semiconductor substrate and patterned to form sidewall spacers on the opposing side surfaces of the gate electrode. A metal layer is then deposited over the gate electrode upper surface, sidewall spacers, and substrate upper surface. The metal layer is heated at a temperature to react the metal with underlying silicon to form metal silicide contacts on the gate electrode and substrate upper surfaces without reducing dopant concentration in the source/drain extensions below a supersaturated dopant concentration. The metal that did not react to form metal silicide is removed.
This invention addresses the need for manufacturing shallow junction semiconductor devices with high conductivity silicide contacts and increased device speed. This invention reduces the possibility of diffusion of dopant from the source/drain regions and extensions. This invention provides a novel and elegant manufacturing method for producing semiconductor devices with supersaturated dopant concentration source/drain extensions.
The foregoing and other features, aspects, and advantages of the present invention will become apparent in the following detailed description of the present invention when taken conjunction with the accompanying drawings.